The Promise of FPGA Engineering

Today's informatics professionals have a wide range of biocomputing options, from peer-to-peer and enterprise grid strategies, server farm and symmetric multiprocessor computing systems or hardware accelerated solutions such as TimeLogic's DeCypher.

Identifying the ideal solution is more than rating CPU speed or processing performance and the burdens placed upon your infrastructure such as heat dissipation, rackspace, power and UPS protection, storage and networking performance. This can require significant input and evaluation time from a wide range of experts within your organization.

When developing our high performance biocomputing solutions, TimeLogic identified Field Programmable Gate Array (FPGA) technology as the ideal way to maximize performance and product lifespan, which brings tremendous reliability and a low total cost of ownership to DeCypher.

TimeLogic's scalable, turnkey solution comes with an Obsolescence Protection Guarantee offer you an ideal biocomputing solution.

Engineering Tradeoffs of ASIC vs. FPGA Design

In contrast to DeCypher's FPGA reconfigurable hardware, some solutions rely on hard-coded ASIC chips. As experienced design engineers, we are familiar with both device technologies, and examined both before initiating our DeCypher development project. We prefer FPGA device technology for the following reasons.

Application Specific Integrated Circuits (ASICs) are ideal for their low production costs (after high initial design costs) when high speed acceleration of a task is needed. However, ASICs force the logic designer to make critical decisions very early in the product's life cycle, at initial design time. One may obtain very high speed by dedicating logic elements on-chip, but losing the flexibility to adapt the circuit operation later. Or, one may choose instead to design-in some degree of generality for later adaptability by incorporating a specialized "microcoded" instruction set. While not as flexible as a general-purpose CPU, such an instruction set preserves (to a degree based on design tradeoffs) the relatively higher speed of ASICs.

This adaptability comes at a cost, however. An ASIC chip that is customized to a specific task, such as Smith-Waterman, can be designed to operate in a single cycle of the system clock, and is thus very fast relative to conventional CPUs in which many cycles are required to implement the algorithm. When the generality of microcode is added to an ASIC, the designer is forced to:

1. Accept that some algorithms will need multiple clock cycles (i.e., multiple instructions) to execute, thus slowing them down;
   
2. Use more of the available chip area than before, reducing the speed otherwise obtained via parallelism; and,
   
3. Predict at the start of product life-cycle the range of instructions needed to implement all anticipated improvements in bioinformatics over the life of the product. The more general the design, the more intrinsic ASIC speed is lost to the design.

Also, ASICs force the designer to select a rigid datapath bit-width intrinsic to the design. If the datapath is too narrow, higher precision data must be doubled-clocked through the device, slowing it down.  If the full datapath width is not needed for a particular algorithm, space on the chip goes wasted: again, effectively slowing the system down if compared to the FPGA approach, which fully utilizes each chip's logic resources and in which path width is set dynamically.

ASICs are ideal for applications that are well-defined and not expected to change during the customer's duration of ownership of the product. The recent history of bioinformatics, however, is characterized by rapid improvement in the state-of-the-art, creating significant risk of early obsolescence for any ASIC based accelerator, even if microcoded.

ASICs are not inherently faster than FPGAs unless they are customized to a specific function, without significant adaptability. The introduction of microcoding negatively affects this intrinsic speed advantage. ASICs and FPGAs are based on identical underlying device physics and similar manufacturing processes.  Both improve over time according to Moore's Law, and yield comparable price-performance improvements over the long haul. One negative factor in low-volume (under 100,000's quantities) ASIC production is the tendency to remain on conservative fabrication rules, such as .35 or .5 micron technology. Since FPGAs are not specific to a particular application, FPGA vendors are manufacturing them in very large quantities, in which it is cost effective to migrate quickly to the best available fabrication technologies.  As a result, finer geometry yields higher speed at lower power dissipation per logic element, contributing to overall system reliability.

FPGA devices are tested "generically" by the FPGA vendor and process variation issues are dealt with by the FPGA vendor, who has made a multi-million dollar investment in these engineering tools and systems.  ASICs manufactured in low volumes on a "contract" fab line may not enjoy the same degree of attention to detail, and the bulk of the burden of testing and device re-engineering falls on the accelerator manufacturer, adversely affecting costs and system pricing.

Advantages of FPGA-Based Accelerators vs. ASICs

DeCypher's use of FPGA based logic permits our design staff to avoid the risks and tradeoffs encountered in ASIC design. Since FPGAs can be rewired "on-the-fly" during in-field use, each algorithm is implemented as a separate "logic configuration file". Each algorithm can run in a single clock cycle (two in some case) at very high speed because each is separately optimized without on-chip constraints imposed by any other algorithm. We control the chip clockrate according to the performance obtainable with each algorithm, independent of any other algorithm.  Similarly, the entire on-chip logical resources of the FPGA can be devoted to maximizing the packing density of a particular algorithm's processing cell independent of other algorithms'. FPGAs do not force a rigid predefined limit on the number of cells per chip.

Switching FPGA wiring between algorithms is brief, and is transparent to the user. Each algorithm's "logic cell" (also called a "processing element" or PE) is as small as possible, maximizing the opportunity for on-chip parallelism. And, new unanticipated algorithms may be easily added to DeCypher by distribution of new data files, as simply as a software update is installed on a conventional computer. In short, FPGAs permit the system designer to dodge the early design tradeoffs associated with fully custom chips. It is not necessary to predict (at significant risk of error) the course of the bioinformatics state-of-the-art early in the product life cycle.

Industry Standard PC Components and FPGAs Yield Enhanced Product Lifecycle Support

FPGAs also aid product support. In the event a logic design flaw is discovered in an ASIC, the hardware must be discarded, generally at a large expense to the vendor, the customer, or both. Two or more months' time is typically required to design, simulate, verify and fabricate corrected chips and circuit boards while the customer waits for a fix. In contrast, FPGA design files may be easily changed and recompiled much like conventional software. There is no time lost waiting for chip fabrication, and in-circuit testing can immediately verify corrected operation. Finally, the corrected configuration file can be downloaded via the Internet and immediately installed on-site without discarding extant hardware.
DeCypher systems are based on a server-farm configuration, in which each internal node (pipeline PC) contains reconfigurable FPGA technology coupled to the fastest CPUs, disk, and RAM available at any given time.  We view these pipelines as a commodity that varies in price-performance over time according to Moore's Law.  As you need to scale up,  you add then-prevailing pipelines to the farm without discarding anything.  Over time, the price-performance of the underlying technology will improve, and we pass that on to you.  By using industry standard PC technology with our FPGA arrays, both we and you enjoy the rapid improvement in price-performance of the PC industry.  Systems that are custom designed and hardwired for the smaller bioinformatics community have much less downward pricing pressure driving their product designs and marketing.

TimeLogic's Obsolescence Protection Guarantee

When improved FPGA chips become compelling and the original FPGAs are phased out of production, our obsolescence guarantee enables customers with continued support contracts to upgrade to new hardware at exceptional savings. Read more about this unique offer.